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MC14008B 4-Bit Full Adder
The MC14008B 4-bit full adder is constructed with MOS P-Channel and N-Channel enhancement mode devices in a single monolithic structure. This device consists of four full adders with fast internal look-ahead carry output. It is useful in binary addition and other arithmetic applications. The fast parallel carry output bit allows high-speed operation when used with other adders in a system.
Features
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* * * * * * *
Look-Ahead Carry Output Diode Protection on All Inputs All Outputs Buffered Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low-Power TTL Loads or One Low-Power Schottky TTL Load Over the Rated Temperature Range Pin-for-Pin Replacement for CD4008B Pb-Free Packages are Available*
PDIP-16 P SUFFIX CASE 648
16 MC14008BCP AWLYYWWG 1
16 SOIC-16 D SUFFIX CASE 751B 1 14008BG AWLYWW
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 1) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value -0.5 to +18.0 -0.5 to VDD + 0.5 10 500 -55 to +125 -65 to +150 260 Unit V V mA mW C C C
A WL, L YY, Y WW, W G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
1
August, 2005 - Rev. 6
Publication Order Number: MC14008B/D
MC14008B
PIN ASSIGNMENT
A4 B3 A3 B2 A2 B1 A1 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD B4 Cout S4 S3 S2 S1 Cin Cin 0 0 0 0 1 1 1 1
TRUTH TABLE (One Stage)
B 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 Cout 0 0 0 1 0 1 1 1 S 0 1 1 0 1 0 0 1
BLOCK DIAGRAM
HIGH-SPEED PARALLEL CARRY B4 15 A4 B3 A3 B2 A2 B1 A1 Cin 1 2 3 4 5 6 7 9 ADDER 4 C4 ADDER 3 C3 ADDER 2 C2 ADDER 1 10 S1 11 S2 12 S3
14
C out
13
S4
VDD = PIN 16 VSS = PIN 8
ORDERING INFORMATION
Device MC14015BCP MC14015BCPG MC14015BDR2 MC14015BDR2G Package PDIP-16 PDIP-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) Shipping 500 Units / Rail 500 Units / Rail 2500 Units / Tape & Reel 2500 Units / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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II I II II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIII IIII I I I I IIII I II I I I I III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II III I I I I I I I I I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIII I I IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I III II IIII III I II II IIII I I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I III II IIII III I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I I I I III II IIII III I II II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIII II IIII I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I I III II IIII I II II IIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIII IIIII I I II II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Total Supply Current (Notes 3 & 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) Quiescent Current (Per Package) Input Capacitance (Vin = 0) Input Current Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) Output Voltage Vin = VDD or 0 (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) (VO = 0.5 or 4.5 Vdc) "1" Level (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Vin = 0 or VDD Characteristic "1" Level "0" Level Source Sink Symbol VOH VOL IOH VIH IDD IOL Cin VIL Iin IT VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 15 -- - 3.0 - 0.64 - 1.6 - 4.2 4.95 9.95 14.95 0.64 1.6 4.2 Min 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- --
2. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk
where: IT is in mA (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.005.
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MC14008B
- 55_C
3 0.1 0.05 0.05 0.05 Max 5.0 10 20 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- - 2.4 - 0.51 - 1.3 - 3.4 4.95 9.95 14.95 0.51 1.3 3.4 Min 3.5 7.0 11 IT = (1.7 mA/kHz) f + IDD IT = (3.4 mA/kHz) f + IDD IT = (5.0 mA/kHz) f + IDD -- -- -- -- -- -- -- -- -- -- -- 0.00001 Typ (Note 2) - 4.2 - 0.88 - 2.25 - 8.8 0.005 0.010 0.015 25_C 0.88 2.25 8.8 2.75 5.50 8.25 2.25 4.50 6.75 5.0 5.0 10 15 0 0 0 0.1 0.05 0.05 0.05 Max 5.0 10 20 7.5 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- - 1.7 - 0.36 - 0.9 - 2.4 4.95 9.95 14.95 0.36 0.9 2.4 Min 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- 125_C 1.0 0.05 0.05 0.05 Max 150 300 600 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- mAdc mAdc mAdc mAdc mAdc Unit Vdc Vdc Vdc Vdc pF
MC14008B
II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I II I I I I I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I III IIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I II I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
Characteristic Symbol tTLH, tTHL VDD Vdc Min Typ (Note 6) Max Unit ns Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 5.0 10 15 -- -- -- 100 50 40 200 100 80 Propagation Delay Time Sum in to Sum Out tPLH, tPHL = (1.7 ns/pF) CL + 315 ns tPLH, tPHL = (0.66 ns/pF) CL + 127 ns tPLH, tPHL = (0.5 ns/pF) CL + 90 ns Sum In to Carry Out tPLH, tPHL = (1.7 ns/pF) CL + 220 ns tPLH, tPHL = (0.66 ns/pF) CL + 112 ns tPLH, tPHL = (0.5 ns/pF) CL + 85 ns Carry In to Sum Out tPLH, tPHL = (1.7 ns/pF) CL + 290 ns tPLH, tPHL = (0.66 ns/pF) CL + 122 ns tPLH, tPHL = (0.5 ns/pF) CL + 90 ns Carry In to Carry Out tPLH, tPHL = (1.7 ns/pF) CL + 85 ns tPLH, tPHL = (0.66 ns/pF) CL + 42 ns tPLH, tPHL = (0.5 ns/pF) CL + 30 ns tPLH, tPHL ns 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 -- -- -- -- -- -- -- -- -- -- -- -- 400 160 115 305 145 110 375 155 115 170 75 55 800 320 230 610 290 220 750 310 230 340 150 110 5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. VDD = -VGS 16 B4 A4 B3 A3 B2 A2 B1 A1 Cin 8 S4 S3 S2 S1 Cout VSS IOH B4 A4 B3 A3 B2 A2 B1 A1 Cin 8 Vout VDD = VGS 16 S4 S3 S2 S1 Cout VSS IOL Vout EXTERNAL POWER SUPPLY EXTERNAL POWER SUPPLY
Figure 1. Typical Source Current Characteristics Test Circuit
Figure 2. Typical Sink Current Characteristics Test Circuit
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MC14008B
VDD 16 B4 A4 B3 A3 B2 A2 B1 A1 Cin 8 500 mF S4 S3 S2 S1 Cout VSS IDD CL CL CL CL
20 ns 90% 10%
20 ns VDD VSS PULSE GENERATOR
Vin
CL
Figure 3. Dynamic Power Dissipation Test Circuit and Waveform
VDD 16 B4 A4 B3 A3 B2 A2 B1 A1 Cin 8 S4 S3 S2 S1 Cout VSS IDD 20 ns Cin 90% 50% 10% tPHL S1 - S4 90% 50% 10% tTHL Cout 50% tPLH tPHL tTLH tPLH 20 ns VDD VSS VOH VOL VOH VOL CL CL CL
PULSE GENERATOR
CL
CL
Figure 4. Switching Time Test Circuit and Waveforms
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MC14008B
Cout
B4
A4 B3
S4
A3 B2
S3
A2 B1
S2
A1 Cin
S1
Figure 5. Logic Diagram
TYPICAL APPLICATION
WORD A + B INPUTS A1 B4 A1 B4 A1 B4 A1 B4
Cin
CHIP 1
Cout
Cin
CHIP 2
Cout
Cin
CHIP 3
Cout
Cin
CHIP 4
Cout
S1
S4
S1
S4
S1
S4
S1
S4
SUM OUTPUTS Calculation of 16-bit adder speed: tP total = tP (Sum to Carry) + tP (Carry to Sum) + 2 tP (Carry to Carry) The guaranteed 16-bit adder speed at 10 V, 25C, CL = 50 pF is: tp total = 290 + 310 + 300 = 900 ns
Figure 6. Using the MC14008B in a 16-Bit Adder Configuration http://onsemi.com
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MC14008B
PACKAGE DIMENSIONS
PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE T
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL.
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
DIM A B C D F G H J K L M S
INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040
MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
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MC14008B
PACKAGE DIMENSIONS
SOIC-16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-A-
16 9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MC14008B/D

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